This guide is for educational purposes only. Use it at your own risk. The procedures described in this guide require advanced knowledge of electronics and very precise soldering. These modifications will certainly void the warranty of the motherboard and the components installed and can permanently damage them. You have been warned.
This guide was possible because of the many people that previously contributed various BP6 modifications. Some of them are (listed in alphabetical order):
Derek "The DareDevil"
What I did was collect all the available articles and datasheets, analyze them, mod an existing BP6 board and compile this guide.
About The Guide:
This is the second part of the guide. I've decided to release it first because it's the most interesting one. The first part of the guide is BP6 board stabilization and will be released soon. You can use the excellent Yoichiro mod if your board voltage stabilization suffers ( http://geta.yoh-tech.com/eng_top.htm ) until my own guide is released (it is based almost entirely on Yoichiro's mod). There will be a second release of this guide that will include more detailed info and pictures. I've decided not to put any pictures of the sockets of my BP6 board since it is a real mess there - I tried much more modifications than described here and there are a lot of connections and soldering that are not really needed.
Some Important Tips:
Use a good soldering iron, providing about 50W of power. I used a cheap soldering iron and managed to break a few motherboard traces and it was a real nightmare to detect and restore. If possible, ground the soldering iron to the motherboard ground (the metal part of the RS232 or printer connectors will do). Remove all the components from the motherboard (CPUs, RAM, cards etc) before soldering. Remove the CMOS battery before soldering. Use a vacuum pump if possible when unsoldering. Try not to apply to much heat when soldering/unsoldering or you will burn the motherboard layers. The best way to remove a socket pin is to disassemble the socket (carefully with a small screwdriver, try not to apply to much force or you will brake the plastic) and melt the solder from the opposite side and the push the pin with the soldering iron a little. It will show a bit from the other side and you will be able to catch it with some tool and pull it out while continuing melting the solder from the opposite side. Always check the connections you make. I did by accident solder two or more pins together because they are to close and I didn't notice until I tried to boot the board. Believe me, the dead motherboard is a very unpleasant thing to see. After I removed the excess solder everything was okay.
The Theory and the Modifications:
PPGA and FC-PGA processors have identical physical characteristics (number of pins and physical dimensions) but that doesn't mean a FC-PGA processor will work with a motherboard that only supports PPGA processors. The reason is that FC-PGA CPUs have a number of new signals and the fact that Intel changed the positions of some of the old pins to make sure that a FC-PGA processor will not run if inserted in a PPGA only board. Another problem for running a Coppermine processor in a PPGA board is the power requirements of this CPU. The Coppermine requires voltages about 1.6-1.75V to operate normally and most PPGA boards are only capable of providing 2V or more which is a bit high for the Pentium III core with its maximum core voltage of 2.1V and will require some pretty serious cooling. Fortunately, the BP6 does not have this limitation and can provide the needed voltages.
I started reading the pile of datasheets and design guides on Intel's website at http://developer.intel.com/ and soon spotted the following differences between the PPGA Celeron and PIII Coppermine / Celeron II processors:
AD36, AB36, Z36 - respectively Vcmos_1.5, Vcmos, Vcmos_2.5 voltages. According to Intel, AD36 has to be connected with the Vtt CPU termination voltage regulator which is 1.5V, Vcmos_2.5 must connect to the 2.5V onboard voltage regulator. The processor itself wires Vcmos either to Vcmos_1.5 or Vcmos_2.5 depending on its type - Celeron PPGA 0.25 micron processors require 2.5V CMOS logic termination voltage and Pentium III and Celeron II 0.18 micron processors require 1.5V. I measured the resistance between pins AB36 and AD36 on the Coppermines and they were indeed internally connected which means we don't need any modifications here. Unfortunately this is not correct. Without connecting Z36 to AB36 (2.5V for Vcmos) the processors won't boot. This is probably due to the design of the BP6 board and I still have no explanation why this happens. There are two groups of CMOS signals - the first voltage of the first one depends on the Vcmos signal, the other one has 2.5V fixed CMOS pull-up. For example, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#, STPCLK#, FERR#, IERR#, THERMTRIP# and PICD[1:0] are 1.5V tolerant for the FC-PGA and 2.5V tolerant for the PPGA and PWRGOOD, BCLK, PICCLK are always 2.5V tolerant and do not depend on the CPU type. Probably Abit wired both groups to 2.5V because the board was not intended to run a CPU that needs 1.5V CMOS pull-up (i.e. the Coppermine). It will be interesting to try to put 2V here since this will put two signal groups in a more reasonable voltage limits and see if this will improve overclocking. Note that before connecting Z36 and AB36, AB36 pin must be removed from the CPU socket or the Vtt 1.5V and 2.5V regulators will be shorted and the board wouldn't be very happy with it.
(Remove AB36 Socket Pin And Connect AB36 To Z36 On Both Sockets)
(Vcmos_1.5 And Vcmos_2.5 Max Ratings)
AG1 - EDGCTRL pin. According to Intel "The EDGCTRL input adjusts the edge rate of AGTL+ output buffers for previous processors and should be pulled up to Vcc core with a 51 ohm 5% resistor. The signal is not used by the Pentium III processor. This pin is required for backwards compatibility. If backwards compatibility is not required, this pin may be left connected to Vcc". So what I did was connect to Vcc core (pin AF2) with a 51 ohm 5% resistor. I was however unable to boot probably because the BP6 already has these resistors (have to check this) so I removed the resistors. No modification necessary here.
(According to Intel AG1 must connect to AF2 with a 51 ohm 5% resistor for backwards processor compatibility. Don't do this on the BP6, the picture is given for reference only)
AH4, X4 - RESET# and RESET2# pins. X4 is defined as RESET# for a PPGA processor and as RESET2# for a FC-PGA processor. AH4 is respectively marked as Reserved on the PPGA and RESET# on the FC-PGA. This is a well known issue, Intel changed the position of the RESET# signal on the Coppermine to ensure it won't reset if inserted in a PPGA only board. The modification that needs to be done is connect AH4 and X4. I've also pulled up AH4 to Vtt using a 150 ohm 1% resistor on both sockets but this is not really needed although this should be done according to Intel.
(Connect AH4 to X4 on Both Sockets)
AM2 - This is another pin that is used by Intel to disable the Coppermine if used in a PPGA only socket. It is grounded on the PPGA and the FC-PGA needs high voltage here (it is marked as Reserved although). What needs to be done here is unsolder/remove the socket pin on both sockets.
(Remove AM2 on Both Sockets)
AN15 - This pin is the BR1# signal on the Celeron. Intel denies the Celeron core is SMP capable so this pin is marked as Reserved in all datasheets. The BR1# signal is used to select the agent in a symmetric multiprocessor system. The corresponding pin on the Coppermine should be X2 according to Intel and is only validated for steppings above or equal to cB0. The position for this signal for stepping below cB0 is N33 according to various reports found on the Internet. At first I though that the AN15 signal must be connected to one of this two pins according to the CPU stepping. However, this is not true. The BR1# pin is actually N33. What needs to be done here is - remove the AN15 socket pin on both sockets in order to break the connection between AN15 processor pin and the motherboard. Connect AN15 motherboard trace to N33 motherboard trace on both sockets to wire the Coppermine BR1# signal.
(Connect AN15 to N33 on Both Sockets)
E27 - SLEWCTRL. The SLEWCTRL input signal provides AGTL+ termination control. The Pentium III processor samples this input to sense the presence of motherboard AGTL+ termination. Intel says to pull down using a 110 ohm 1% tolerance resistor. I did this on both sockets. However, the board will run perfectly without these resistors, and therefore this modification is not needed.
(Connect E27 to F32 using a 110 ohm 1% Tolerance Resistor on Both Sockets)
G35 - This pin is marked as Reserved on the PPGA and must be connected to Vtt regulator on FC-PGA processors. It is used to provide the level of voltage terminating signal Vtt. Connect G35 to G37 (Vtt).
(Connect G35 to G37 on Both Sockets)
S35 - RTTCTRL. This signal is used to control the value of the processor on-die termination resistance and provides AGTL+ termination control. The Pentium III processor samples this input to sense the presence of motherboard AGTL+ termination. According to Intel, this pin must be pulled down to ground using a 68 ohm 1% tolerance resistor for dual processor systems. However I found out that resistors with this value introduce a lot of lockups and instability. The values I suggest are either 330 ohm or leave unconnected. If this pin is not connected, a single FC-PGA Coppermine is able to run rock stable at 124MHz FSB. It only reaches 110MHz FSB if a 68 ohm resistor is used. My dual Coppermines run very stable with 330 ohm resistors. However this is an area that needs more investigation. I suspect RTTCTRL and SLEWCTRL are the pins that need more modifications in order to run dual PIIIs at speeds above or equal to 124MHz FSB. The other possible values for RTTCTRL pull down are 62, 110, 150 ohm. I tried them all - 330 ohm or no connect are the best so far.
(Connect S35 to P32 using a 330 ohm Resistor on Both Sockets)
(Typical RTTCTRL Values)
Y33 - CLKREF, input reference voltage. When using single-ended clocking mode, the BCLK#/CLKREF signal on the processor servers as a reference voltage to the clock input. To provide a steady reference voltage, a filter circuit (a capacitor) must be implemented and attached to this pin.
On the bp6, this pin is grounded since this signal is not used by the Celeron PPGA processor. However, for the Pentium III processor, the voltage reference must be attached or the processors will not be able to sync properly. I've seen a lot of posts on the Internet about the CLKREF implementation on various socket adapters. For example, there was a poorly designed S370 to Slot1 adapter that didn't implement the CLKREF circuit and 133MHz CPUs were only able to work stable at 100MHz FSB and below. I'm pretty sure the voltage circuit is needed for dual CPUs to work stable above 100MHz FSB. The reference voltage is not needed for a FC-PGA Celeron however. What has to be done here is break the connection of the socket pin with ground and implement the voltage divider using two 110 ohm 1% tolerance resistors and a 4.7uF capacitor. Breaking the ground connection is tricky since it is connected to the internal motherboard ground plane (the bp6 has four planes, the two inner are mainly ground and voltage islands as recommended by Intel). First, the socket pin must be carefully unsoldered and then the motherboard hole must be drilled to completely remove the ground connection and make some space for the insulation and the wire that will be soldered here. After the hole is drilled, solder a short wire to the pin, insulate it and reinsert it back in the socket. I used some glue to hold it there. Then you can safely implement the voltage circuit. Use Z36 as the 2.5V source.
AA33, AA35, AN21, E23, S33, S37, U35, U37 - These Vtt pins must be left unconnected (NC) for backwards compatibility with Celeron processors (CPUID 066xh). For designs which do not support the Celeron processors (CPUID 066xh), and for compatibility with future processors, these Vtt pins should be connected to the Vtt plane. For dual processor designs, these pins must be connected to Vtt. I tried connecting all these pins to the Vtt regulator. The only effect was higher stress on the LM338 Vtt regulator - it became about 10 degrees C hotter. Since this mod didn't introduce any stability improvements I removed the connections. My advice is to leave these pins not connected.
(Pins That Must Be Connected To Vtt. Leave Unconnected Or Connect To Vtt If You Want)
Some Interesting Reading:
1. Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
- http://developer.intel.com/design/penti ... 249658.htm
2. Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide Update
- http://developer.intel.com/design/penti ... 298647.htm
3. Intel Celeron Processor up to 1.10 GHz Datasheet
- http://developer.intel.com/design/celer ... 243658.htm
4. Intel Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
- http://developer.intel.com/design/penti ... 245264.htm
5. Intel 440BX AGPset / PGA370 Scalable Performance Board Design Guide
- http://developer.intel.com/design/intar ... 273296.htm
6. Intel 440BX AGPset Design Guide
- http://developer.intel.com/design/chips ... CG+devside&
7. Intel 440BX AGPset Design Guide Update
- http://developer.intel.com/design/chips ... CG+devside&
8. Intel 440BX AGPset Design Guide Update
- http://developer.intel.com/design/chips ... CG+devside&
9. PGA370 Processor Bus Terminator Design Guidelines
- http://developer.intel.com/design/penti ... 248693.htm
10. VRM 8.4 DC-DC Converter Design Guidelines
- http://developer.intel.com/design/penti ... 35_006.htm
11. VRM 8.5 DC-DC Converter Design Guidelines
- http://developer.intel.com/design/penti ... 249659.htm
12. How to solder